1. Field of the Invention
The present invention relates to an apparatus for generating address bit patterns for testing semiconductor memory devices by supplying address data to semiconductor memory devices for the purpose of testing the same.
2. Description of the Related Art
For a better understanding of the present invention, description will first be made of a semiconductor memory device test pattern generating apparatus known heretofore by referring to FIG. 2 of the accompanying drawings. As can be seen from the figure, the test pattern generating apparatus is comprised of a pattern generator 1, an X-address bit selector circuit 2, a Y-address bit selector circuit 3, an X-address translation/memory circuit 4, and a Y-address translation/memory circuit 5.
The pattern generator 1 is so designed as to output (m+1) X-addresses 11 in the form of X-address data X.sub.0, X.sub.1, . . . , X.sub.m as well as (m+1) Y-addresses 12 in the form of Y-address data Y.sub.0, Y.sub.1, . . . , Y.sub.m, respectively. Both of these X- and Y-address data 11 and 12 are supplied to the X-address bit selector circuit 2 and the Y-address bit selector circuit 3, respectively. The X-address selector circuit 2 selects optionally given address data from the X-addresses data 11 and the Y-address data 12 inputted thereto, to thereby supply (n+1) selected X-address signals 13 to the X-address translation/memory circuit 4 as the selected X-address data SX.sub.0, SX.sub.1, . . . , SX.sub.n.
Similarly, the Y-address bit selector circuit 3 selects optionally given address data from the X-address data 11 and the Y-address data 12 as inputted, whereby (n+1) selected Y-address signals 14 are supplied as the selected Y-address data SY.sub.0, SY.sub.1, . . . , SY.sub.n to the Y-address translation/memory circuit 5. In response to the input of the selected X-address signals 13, corresponding address data written previously in the X-address translation/memory circuit 4 are read out, resulting in that (p+1) stored X-addresses 17 are Generated as the memory X-address data MX.sub.0, MX.sub.1, MX.sub.p.
On the other hand, from the Y-address translation/memory circuit 5, those of the address data are read out which correspond to the selected Y-address signals 14, whereby (p+1) memory Y-addresses 18 are outputted as the memory Y-address data YM.sub.0, YM.sub.1, . . . , YM.sub.p. The memory X-addresses 17 and the memory Y-addresses 18 are supplied as the X-address signal and the Y-address signal to a memory device under test to make access to the memory cells of thereof.
In general, in a semiconductor memory device, the address signals applied to external address terminals of the memory device differ from the address signals actually transmitted to the memory cells of a memory cell array incorporated in the memory device. More specifically, the address signals supplied to the external address terminals usually undergo once an address translation, whereon the address signals resulting from the translation are transmitted to the memory cell array. In this conjunction, there is known a peculiar address translation scheme in which the method for column address translation differs from that for the row address translation on a row-address basis. Furthermore, such a particular address translation may also be realized by selecting optionally the X-address data X.sub.0, X.sub.1, . . . , X.sub.m and the Y-address data Y.sub.0, Y.sub.1, . . . , Y.sub.m outputted from the pattern generator 1 by means of the X-address bit selector circuit 2 and the Y-address bit selector circuit 3 and supplying these selected address data to the X-address translation/memory circuit 4 and the Y-address translation/memory circuit 5, respectively. Parenthetically, the circuit configuration shown in FIG. 2 is disclosed in Japanese Unexamined Patent Application Publication No. 246100/1985 (JP-A-60-24100).
Now, let's consider, by way of example, a semiconductor memory device of such a configuration as shown in FIG. 3. This memory device 101 is assumed as being constituted by 64 memory cells arrayed in a matrix of eight rows and eight columns. In general, for making access to the memory cells a.sub.0, a.sub.1, . . . , a.sub.63, there are used X-address bit data AX.sub.0, AX.sub.1 and AX.sub.2 and Y-address bit data AY.sub.0, AY.sub.1 and AY.sub.2 which are represented by first to sixth bits, respectively, of a binary digit together with address data representing in a binary notation a suffix "k" of the memory cell ID a.sub.k (where k=0, 1, . . . , 63), whereby memory cells a.sub.k to be addressed can be designated. On these conditions, when the memory cells a.sub.0 to a.sub.63 are to be sequentially addressed, the address bit data AY.sub.2, AY.sub.1, AY.sub.0, AX.sub.2, AX.sub.1 and AX.sub.0 are changed in such a manner as is illustrated in FIG. 4.
At this juncture, it should however be noted that a column address decoder 103 dedicated for decoding the X-address data inputted to an external terminal 102 may be configured as shown at 104 in FIG. 3 when AY.sub.2 ="0" while being configured as shown at 105 when AY.sub.2 ="1". More specifically, when AY.sub.2 ="0", the address data AX.sub.0 is inverted upon decoding, while the address data AX.sub.1 as decoded is inverted when AY.sub.2 ="1". On the other hand, a row address decoder 107 for decoding the Y-address data inputted to the external terminal 106 is implemented in such a configuration as shown at 108, as in the case of the conventional decoder.
Such being the circumstances, in order to allow the memory cells a.sub.0, a.sub.1, . . . , a.sub.63 of the semiconductor memory device 101 to be sequentially addressed or accessed, it is required to change the X-address data AX.sub.0, AX.sub.1 and AX.sub.2 supplied to the external terminal 102 and the Y-address data AY.sub.0, AY.sub.1 and AY.sub.2 supplied to the external terminal 106 in such a manner as illustrated in FIG. 5. With the structure of the semiconductor memory device 101 described above, it is intended to avoid the use of a concentrated power supply circuit for the memory accessing operation. Of course, the memory structure differs in dependence on the method or process adopted in manufacturing the same.
Thus, by setting the states of the address bit selector circuits 2 and 3 in correspondence to the column address decoder 103 and the row address decoder 107 of the semiconductor memory device 101 under test and writing the contents of the address translation/memory circuits 4 and 5, it is possible to establish coincidence between the addresses generated by the pattern generator 1 and the addresses designating the memory cells of the cell array incorporated in the semiconductor memory device 101 under test.
FIG. 6A illustrates the selecting operation of the X-address selector circuit 2 shown in FIG. 2, and FIG. 6B illustrates the operation of the Y-address bit selector circuit 4 also shown in FIG. 2. Further, the content of the X-address translation/memory circuit 4 is shown in FIG. 7A, while that of the Y-address translation/memory circuit 5 is shown in FIG. 7B. Connection between the memory address outputs 17 and 18 (FIG. 2) and the external terminals 102 and 106 (FIG. 3) are illustrated in FIG. 8.
The semiconductor memory device test pattern generating apparatus described above suffers not a few problems. First, in the case of semiconductor memory device of a large capacity which are increasingly employed in practical applications, the method of allocating the column addresses may differ in dependence on the row addresses. Further, in the case of a memory device susceptible to a multi-bit parallel test, the conditions for translation of the addresses to be supplied to the semiconductor memory device in the test mode may differ from the translation conditions in the normal operation mode. At this juncture, it is noted that with the address translation effected by the test pattern generating apparatus known heretofore, the conditions for the address translation was limited only to a single specification. In other words, the address translation condition once established could not be changed or altered. Besides, it is noted that although the set states of the X- and Y-address bit selector circuits 2 and 3 and the data placed in the X- and Y-address translation/memory circuits 4 and 5 can be altered, it takes intolerably a lot of time, incurring degradation in the efficiency of the inspection or test of the memory device. It should further be pointed out that the conditions for the address translation can not be changed on a real-time basis in the course of the inspection or test.